Among display apparatuses, a liquid crystal display apparatus is a thin type display and has characteristics such as low power consumption. In particular, a liquid crystal display apparatus including an active matrix substrate provided with a switching element such as a thin film transistor (TFT) for each pixel has a high contrast ratio and excellent response characteristics, and exhibits a high performance. Therefore, such an apparatus is suitably used in a television receiving apparatus, a personal computer or the like.
The active matrix substrate includes a plurality of gate wirings (scanning lines), and a plurality of source wirings (signal wirings) intersecting each gate wiring through an interlayer insulating film, which are formed thereon, and thin film transistors for switching pixels are provided in the vicinity of intersecting portions of the gate wirings and the source wirings (for example, Japanese Patent Laid-open Publication No. 2008-153688, etc.). Since a capacitance (parasitic capacitance) formed at the intersecting portion of the gate wiring and the source wiring causes a deterioration in display quality, it is preferable to reduce the capacitance, and an interlayer insulating film including a spin on glass (SOG) material is formed on the intersecting portions. In the active matrix substrate of Japanese Patent Laid-open Publication No. 2008-153688, the interlayer insulating film is made of the SOG material containing a siloxane composition having a Si—O—C bond as a skeleton.
In Japanese Patent Laid-open Publication No. 2008-153688, as the siloxane composition, specifically, there are a composition in which a siloxane oligomer and a void-forming material are uniformly dissolved in an organic solvent (Japanese Patent Laid-open Publication No. 2001-98224), and
a composition containing a silicon resin represented by a general formula below as a main agent:(HR2SiO1/2)x(SiO4/2)1.0 
(wherein R is a hydrogen atom, or a group selected from a group consisting of an alkyl group and an aryl group, and X is 0.1≤X≤2.0) (Japanese Patent Laid-open Publication No. H6-240455).
FIG. 15 is a schematic cross-sectional view illustrating an example for a structure of a portion of a conventional active matrix substrate 60, in which a TFT 61 is formed.
As illustrated in FIG. 15, a gate electrode 11a (forming a part of a gate wiring 11) and a capacitance wiring 13 are formed on an insulating substrate 10 made of glass of the active matrix substrate 60.
An interlayer insulating film 14 is formed on the insulating substrate 10 so as to cover the same. The interlayer insulating film 14 is made of the SOG material containing the above-described siloxane composition and the like. On the gate electrode 11a and on the capacitance wiring 13, portions other than the respective end edge parts thereof are not covered with the interlayer insulating film 14, and opening parts Ca and Ca are formed therein. A gate insulating film 15 is formed on the interlayer insulating film 14, and a semiconductor film 16 is formed on a portion of the gate insulating film 15 corresponding to the opening part Ca on the gate electrode 11a side. In addition, an n+ film 17 is formed on the semiconductor film 16 so as to cover the same, a source region and a drain region are formed therein, and a source electrode 18 and a drain electrode 19 are formed on the source region and the drain region. The TFT 61 is constituted by the gate electrode 11a, the gate insulating film 15, the semiconductor film 16, the n+ film 17, the source electrode 18, and the drain electrode 19.
In addition, a passivation film 21 is formed on the source electrode 18 and the drain electrode 19 so as to cover the same, and an interlayer insulating film 22 including an organic material is formed on the passivation film 21 so as to cover the same.
Further, in the opening part Ca on the capacitance wiring 13 side, a capacitance electrode 20 is formed on the gate insulating film 15. A pixel electrode 23 is formed in an opening part Cb on the capacitance electrode 20.
FIG. 16 is a flowchart illustrating a processing procedure for forming the interlayer insulating film 14.
An SOG material is applied to the insulating substrate 10, the gate wiring 11, and the capacitance wiring 13 to form a coating film (S11).
After forming the coating film, the coating film is baked to adjust a thickness thereof (S12).
After the bake, a photoresist material is applied to the coating film to form a resist (S13).
The resist is exposed to light using a photomask (S14), and is developed (S15) to form a resist pattern.
Next, a portion of the coating film which is not covered with the resist is subjected to etching such as dry etching using, for example, a mixed gas of carbon tetrafluoride and oxygen (S16) to form the opening parts Ca.
Finally, the resist is removed (S17).